This application claims the priority benefit of Taiwan application serial no. 88121972, filed Dec. 15, 1999.
1. Field of Invention
The present invention relates to a bus transaction method, and more particularly, relates to a data transaction method between the control chipsets in a computer system and an arbitration method between the control chipsets.
2. Description of Related Art
FIG. 1 shows a PCI bus system connecting various components of a conventional computer system. As shown in FIG. 1, a central processing unit 10 is coupled to the PCI bus 14 via a host bridge 12. The master controller of PCI compatible peripheral devices such as a graphic adapter 16a, an expansion bus bridge 16b, a LAN adapter 16c and a SCSI host bus adapter 16d are also coupled to the PCI bus 14. Each master controller sends out a request (RST) signal demanding the use of the PCI bus 14. The host bridge 12 serves as an arbitrator that sends out grant (GNT) signals to the controller when the PCI bus 14 is available.
Data transmission between PCI compatible devices (such as the master controllers or the north bridge) is controlled by a few interface control signals. A cycle frame (FRAME) is issued from an initiator (the master controller or the north bridge), indicates the initialization of a data access operation and the duration therein. As soon as the FRAME signal is sent out, data transaction via the PCI bus begins. A low FRAME signal indicates data transmission is in progress. After the initiation of data transaction, the address bus AD sends out a valid address during the address cycle. In the meantime, the command/byte enable (CBE[3:0]) signal lines send out a valid bus command (according to PCI specification) for informing the target device the data transaction mode demanded by the initiator. In general, the four bits of the command/byte enable signal lines code up to a maximum of 16 different commands, and each command is defined in detail in the PCI specification. After the effective address is sent out, a data cycle begins in which data is transmitted through the address bus AD. In the meantime, byte enable signals are sent so that data can be transmitted. When the transmission of FRAME signal stops, the last set of data is transmitted and there is no more transaction. An initiator ready (IRDY) signal and a target ready (TRDY) signal are used in couple by the system for displaying the readiness of the initiating device and the target device in data transaction. In a data read operation, the IRDY signal indicates that the initiator is ready to receive the demanded data. In a data write operation, the TRDY signal indicates that the target device is ready to receive the demanded data. A stop (STOP) signal is used by the target device to request a termination of data transaction from the initiator.
FIG. 2 is a timing diagram showing the various signals in the PCI bus interface during a read operation. The period within which data are transmitted via the PCI bus is known as a bus transaction cycle 20. The bus transaction cycle 20 includes an address cycle 22 and several data cycles, for example, 24a, 24b and 24c. Each data cycle 24a/b/c can be further divided into a wait cycle 26a/b/c and a data transfer cycle 28a/b/c. The following is a brief description of the PCI bus interface during a read operation for illustrating the control signals according to PCI specification.
At cycle T1, an initiator (master) sends a request signal REQ for accessing the PCI bus. At this time, if there is no other device having high priority requesting accessing the PCI bus, then during cycle T2, the main bridge (arbitrator) sends a grant signal GNT for allowing the initiator accesses the PCI bus. During cycle T3, a FRAME signal is sent by the initiator for indicating the start of a data transaction while a start address is put on the address bus AD lines to locate the target device of the transaction. In the meantime, a read command is transmitted through the CBE lines. After the delivery of the read command, a byte enable signal is put on the CBE lines. The byte enable signals are sent throughout the data cycles (including 24a, 24b and 24c). During cycle T4, the initiator submits an initiator ready signal IRDY indicating readiness for data transmission. However, the target device is still not ready yet. Hence, the target device keeps preparing data while the initiator idles in the wait cycle 26a of the data cycle 24a. During cycle T5, the target device already prepares all the necessary data for transmission, thereby sending out a target ready TRDY signal. Therefore, in data cycle 28a, both IRDY and TRDY are out and the initiator begins to read data from the target device. During cycle T6, the target device no longer issues the target ready TRDY signal, and the transmission of the first set of data is completed. Meanwhile, another set of data is prepared by the target device. Again, the initiator idles in a wait cycle 26b of the data cycle 24b. During cycle T7, the target ready TRDY signal is again issued for indicating the second set of data is ready. In the cycle 28b, both the IRDY and TRDY are issued and the initiator begins to read data from the target device. If the initiator has insufficient time to read all the data from the target device, the IRDY signal terminates. Since the TRDY signal is still out, the wait cycle 26c is activated by the initiator. As soon as the initiator is ready again as in cycle T9, the IRDY signal is re-issued. The initiator reads data from the target device during data transfer cycle 28c when both IRDY and TRDY signals are issued, and thereby a single read operation is completed.
To carry out proper data transaction according to the conventional PCI specification, complicated control signals, wait states, arbitration steps must be used. Typically, about 45 to 50 signaling pins are required according to the PCI specification. In general, complicated procedure is unnecessary for internal transaction between control chipsets. Hence, to speed up internal transaction between control chipsets, a simplified transaction method that adheres to the conventional PCI specification is needed.
However, transactions between control chips of a PC generally do not use all of the complicated functions provided by the PCI specification. The performance between the control chips is usually decreased by unnecessary procedure. As the device integration increases, the control chips may be integrated to a single chip and more functions are provided. For example, the CPU, north bridge and the south bridge are formed integrally into a single chip. Therefore, pins of the chip package become more important. In order to increase the seed of transactions between the control chips, a simplified and specific specification for use between the control chips is required.
The present invention provides a control chips, data transaction method between control chips within the control chipset and a bus arbitration method between the control chips within the control chipset. Therefore, the performance of the control chipset increases, and types and numbers of signal lines between the control chips are reduced.
The present invention provides a data transaction method between control chips. The data or commands are continuously transmitted without any waiting, stop or retry.
The present invention provides a data transaction method between control chips within the control chipset, wherein cycles for waiting stop/retry are reduced.
The present invention provides a bus arbitration method between control chips which reduces arbitration and grant time.
According to the present invention, data buffers of the control chips of the control chipset have fixed size and amount. In addition, read/write acknowledge commands are asserted in sequence according to read/write commands, by which the control chips can detect the status of the buffers within other control chips. When a control chip asserts a command, the corresponding data must be prepared in advance. Therefore, the signal line for providing the waiting status, data transaction cycle and stop/retry protocol can be omitted. Accordingly, commands or data can be continuously transmitted without waiting, stop or retry, and the performance is increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.